Typically, fuse circuit structures are used in Application Specific Integrated Circuits (ASIC) for permanently storing a bit of information. There are more and more applications where it is desirable to use a fuse to store data (e.g. storing defective addresses in Built-In-Self-Repair, storing a unique identification number for some chips, etc.). A basic fuse is just a metal wire on the chip, where one end of the metal wire is connected to one of the logic levels and the other end of the metal wire is used to read the logic level. If the connected logic level is not desired, the end of the metal wire is blown using a laser machine. When the fuse is blown, the other end of the fuse will appear as floating logic. Hence, some circuitry must be used to provide opposite data for the open circuit.
A prior art fuse circuit structure design is illustrated in FIG. 1. Specifically, the fuse circuit structure is shown within the dotted box 10, and the remaining circuitry 20 is configured to read and hold the coded value in the fuse once it is coded. As shown, the design requires an extra flip flop to hold the data.
When the ENABLE signal is active:
If the fuse is blown, then the value at node D (the output 22 of the fuse) is "1" and when a clock edge is provided, the D value would go through multiplexer 24 and get stored in the first half-latch. The ENABLE signal can then be turned off.
If the fuse is not blown, then the value at node D (the output 22 of the fuse) is "0" and when a clock edge is provided, the D value would go through multiplexer 24 and get stored in the first half-latch. The ENABLE signal can then be turned off.
Once the coded value is read, the ENABLE signal is turned off. Even if the circuit is being clocked (CLK remains ON), then the stored value is fed back through the multiplexer xx and the read value is not effected.
A disadvantage to the circuitry illustrated in FIG. 1 is that it requires the ENABLE signal to be kept ON for almost one half of the clock cycle, during which there is a direct path from VDD to VSS. This results in significant power consumption. Moreover, when the ENABLE signal is turned off, the circuitry requires a feedback path to store the coded and read data from the fuse. As shown in FIG. 1, the latch or flip-flop circuitry requires a number of transistors. If a simple and regular latch circuit is used at the output, the transistors used in the fuse circuit would need to be large in order to change the data inside the latch. Due to its static current, the latch circuit could burn the unblown fuse if it is enabled for a long enough period of time.
Another prior art fuse circuit structure design is illustrated in FIG. 2. As shown, the structure uses a half latch circuit 30 that includes three transistors. When the fuse is not blown, the output will have logic 1, and when the fuse is blown, the output will have logic 0 (when power is up). As shown in FIG. 2, no flip-flop is needed to hold the data. The circuitry shown in FIG. 2 also consumes significant power when the ENABLE signal is turned on because it would have a direct path from VDD to VSS.
Still other prior art suggests removing the transistor which connects to the ENABLE signal and relies on a capacitance divider to ensure that the circuit arrives in the correct state. However, since a half latch is used, it is possible that the incorrect output is generated if there is high ohm leakage resistance at the input of the inverter. The high ohm leakage resistance can "pull down" the inverter input to logic 0 before the feedback transistor turns on and supports pulling up the input of the inverter when the power is on.